TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 339

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

data bit determination of 0 or 1 are applied regardless of whether a signal has a leader or not. Thus
receivable remote control signals are limited.
RMCRCR2 <RMCLD>, RMC starts receiving data if it recognizes a signal of which low width is shorter
than a maximum low width of leader detection specified in the RMCRCR1 <RMCLLMAX7:0> bits. RMC
keeps receiving data until the final data bit is received.
14.3.1.7 Stopping Reception
14.3.1.8 Receiving Remote Control Signal without Leader
RMCRCR2 register <RMCLD>=1
RMC stops reception by clearing the RMCREN <RMCREN> bit to “0” (reception disabled).
Clearing this bit during reception stops reception immediately and the received data is discarded.
Setting RMCRCR2 <RMCLD> enables RMC to receive signals with or without a leader. By setting
If RMCRCR2 <RMCLD> is enabled, the same settings of error detection, reception completion and
Waiting
leader
for
Under development
Page327
Leader waveform
Maximum data bit cycle < RMCDMAX7:0>
Maximum data bit cycle is detected if a
signal stays low shorter than specified and
longer than a maximum data bit cycle.
Minimum low width <RMCLLMIN7:0>
A waveform of which low width is
shorter than specified is
determined as the beginning of
data. RMC starts data reception.
TMPM330