TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 414
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Company
Part Number
Manufacturer
Quantity
Price
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18 Flash Memory Operation
Boot ROM
(Note 1) FD/ FY/ FW in the above table denotes the TMPM330FDFG, TMPM330FYFG and
(Note 2) In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be
(Note 3) In case of any negative acknowledge, the boot program returns to a state in which it waits
(Note 4) The RAM actual end address of the TMPM330FYFG is 0x2000_3FFF.
(Note 5) The flash memory actual end address of the TMPM330FYFG is 0x3F83_FFFF.
(Note 6) The actual number of the TMPM330FYFG flash blocks is one.
(Note 1) In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be
(Note 2) In case of any negative acknowledge, the boot program returns to a state in which it
TMPM330FWFG respectively.
1/16 of the desired baud rate.
for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a
negative acknowledge does not occur.
In addition to 256KB flash area, the TMPM330FYFG provides 128-word data/ password
area (0x3F87_FF00 – 0x3F87_FF80, 1 page) for Show Product Information command.
1 byte
2 byte
3 byte
4 byte
5 byte
6 byte
7 byte
8 byte
1/16 of the desired baud rate.
waits for a command code (3rd byte). In I/O Interface mode, if a communication error
occurs, a negative acknowledge does not occur.
Table 18-9 Transfer Format for the Chip and Protection Bit Erase Command
Byte
Data Transferred from the Controller
Serial operation mode and baud rate
For UART mode
For I/O Interface mode 30H
Command code
Chip erase command code
(Wait for the next command code.)
to the TMPM330
⎯
⎯
⎯
⎯
Under development
86H
Page402
(40H)
(54H)
Desired baud
rate (Note 1)
Baud rate
Data Transferred from the TMPM330 to
-Normal acknowledge
(The boot program aborts if the baud rate
can not be set correctly.)
-Communication error
ACK for the chip erase command code byte
-Normal acknowledge
-Negative acknowledge
ACK for the serial operation mode byte
For UART mode
-Normal acknowledge 86H
For I/O Interface mode
ACK for the command code byte (Note 2)
-Normal acknowledge
-Negative acknowledge
-Communication error
ACK for the command code byte (Note 2)
-Normal acknowledge
-Negative acknowledge
the Controller
⎯
⎯
⎯
⎯
TMPM330
30H
× 1H
× 1H
× 8H
40H
54H
4CH
4FH
× 8H
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