TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 82

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8 Exceptions
(6)
(7)
Configuring the clock generator
Enabling interrupt by CPU
and enable interrupts in the IMCG register of the clock generator. The IMCG register is capable of
configuring each source.
avoid unexpected interrupt. To clear corresponding interrupt request, write a value corresponding
to the interrupt to be used to the ICRCG register. See 8.6.3.5 CG Interrupt Request Clear Register
for each value.
not used for clearing a standby mode. However, an “H” pulse or “H”-level signal must be input so
that the CPU can detect it as an interrupt request.
interrupt with the Interrupt Set-Enable Register. Each bit of the register is assigned to a single
interrupt source.
Writing “1” to the corresponding bit of the Set-Enable Register enables the intended interrupt.
Clear-Pending Register is not needed as this operation will cause an interrupt request to be
cleared.
● Clock generator register
IMCGn<EMCGm>
ICRCG<ICRCG>
IMCGn<INTmEN>
(Note)
●NVIC register
Interrupt Clear-Pending<m>
Interrupt Set-Enable<m>
(Note)
Before enabling an interrupt, clear the corresponding interrupt request already held. This can
Interrupt requests from external pins can be used without setting the clock generator if they are
For an interrupt source to be used for clearing a standby mode, you need to set the active state
Enable the interrupt by the CPU as shown below.
Clear the suspended interrupt in the Interrupt Clear-Pending Register. Enable the intended
Writing “1” to the corresponding bit of the Clear-Pending Register clears the suspended interrupt.
If the Interrupt Set-Pending Register is used for generating an interrupt, setting of the
n: register number
m: number assigned to interrupt source
m: corresponding bit
Under development
←
←
←
Active state
Value corresponding to the interrupt to be used
“1” (interrupt enabled)
Page70
←
←
“1”
“1”
TMPM330