TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 182

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10 16-bit Timer/Event Counters (TMRBs)
10.5.4
10.5.5
10.5.6
10.5.7
10.5.8
10.5.9
TB0CP0 and TB0CP1 capture registers. The timing with which to latch data is specified by
TB0MOD <TB0CPM1:0>.
specifically, UC0 values are taken into the TB0CP0 capture register each time “0” is written to
TB0MOD<TB0CP0>.
(TB0RUN<TB0PRUN> = “1”).
capture register, use a 16-bit data transfer instruction or read in the order of low-order bits
followed by high-order bits.
by reading the TB0U
up-counter with set values of the TB0RG0 and TB0RG1 timer registers. If a match is detected,
INTTB0 is generated.
signal to the capture registers.
TB0FFCR<TB0C1T1, TB0C0T1, TB0E1T1, TB0E0T1>.
writing “00” to TB0FFCR<TB0FF0C1:0>. It can be set to “1” by writing “01,” and can be cleared
to “0” by writing “10.”
enable timer output, the port I related registers PICR and PIFR1 must be programmed
beforehand.
the UC0 up-counter into the TB0CP0 and TB0CP1 capture registers. The interrupt timing is
specified by the CPU.
Capture
Capture Registers (TB0CP0H/L, TB0CP1H/L)
Up-counter capture register (TB0UCH/L)
Comparators (CP0, CP1)
Timer Flip-flop (TB0FF0)
Capture interrupt (INTCAP00, INTCAP01)
This is a circuit that controls the timing of latching values from the UC0 up-counter into the
Software can also be used to import values from the UC0 up-counter into the capture register;
These are 16-bit registers for latching values from the UC0 up-counter. To read data from the
Other than th
These are 16-bit comparators for detecting a match by comparing set values of the UC0
The timer flip-flop (TB0FF0) is reversed by a match signal from the comparator and a latch
The value of TB0FF0 becomes undefined after a reset. The flip-flop can be reversed by
The value of TB0FF0 can be output to the timer output pin, TB0OUT (shared with PI0). To
Interrupts INTCAP00 and INTCAP01 can be generated at the timing of latching values from
e capturing functions shown above, the current count value of the UC0 can be captured
C registers.
To
Under development
use
It can be enabled or disabled to reverse by setting the
Page170
this
capability,
the
prescaler
must
be
TMPM330
running