TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 335

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

Example: Threshold of 0/1 determination is set to 2.5T with the <RMCDATL6:0> bit.
(3)
(4)
Data bit
waveform
Threshold of 0/1
determination
Determination
result
exceeds the threshold, the bit is determined as “1”. If not, the bit is determined as “0”.
interrupt can be generated in each falling edge of the data bit. Using this interrupt together with a
16-bit timer enables the determination to be done by software.
a Remote Control Signal in a Phase Method”.
<RMCDMAX7:0> bits. If the falling edge of the data bit cycle isn’t monitored after time specified as
threshold in the <RMCDMAX7:0> bits, a maximum data bit cycle is detected. The detection completes
reception and generates an interrupt.
<RMCLL7:0> bits. After the falling edge of the data bit is detected, if the signal stays low longer than
specified, excess low width is detected. The detection completes reception and generates an
interrupt.
Based on a falling edge cycle, the data bit is determined as 0 or 1.
Configure a threshold of the determination with the RMCRCR3 <RMCDATL6:0> bit. If the cycle
By setting ”1” to the RMCRCR2 <RMCEDIEN> bit, a remote control signal input falling edge
The following shows how the data bit is determined as “0” or “1”.
As for data bit determination of a remote control signal in a phase method, see 14.3.1.10 “Receiving
To complete data reception, settings of detecting the maximum data bit cycle and excess low width
are required. If multiple factors are specified, reception is completed by the factor detected first.
Make sure to configure the reception completion settings.
1) Completed by a maximum data bit cycle
To complete reception by detecting a maximum data bit cycle, you need to configure the RMCRCR2
2) Completed by excess low width
To complete reception by detecting the low width, you need to configure the RMCRCR2
Settings of Data Bit Determination
Settings of Reception Completion
T
T
Under development
Remote control input falling edge interrupt
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“0”
T
T
T
“1”
T
T
“0”
T
T
TMPM330