TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 60
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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7 Clock/Mode Control
7.6.4
7.6.5
(Note 1)
(Note 2)
(Note 3)
(Note)
Processor core
I/O port
TMRB
RMC
RTC
CG
PLL
High-speed oscillator (fc)
Low-speed oscillator (fs)
ADC
SIO
SBI
WDT
CEC
functions, “○” and “×” indicate that clock is supplied and is not supplied respectively.
STBYCR<STBY2:0>.
Table 7-7 shows the mode setting in the <STBY2:0>.
Table 7-8 show the operational state in each mode.
The low power consumption mode is specified by the setting of the standby control register
For I/O port, “○” and “×” indicate that input/output is enabled and disabled respectively. For other
Low power Consumption Mode Setting
Operational State in Each Mode
○: Operating, ×: Stopped
In the SLOW mode, the ADC, SIO, SBI, TMRB and WDT cannot be used and must be
stopped.
The high-speed oscillator does not stop automatically and must be stopped by setting
the OSCCR1<XEN> bit.
The state depends on the SYSCR2<DRVE> bit.
Block
Do not set any value other than those shown above in <STBY2:0>.
Table 7-7 Low power consumption mode setting
NORMAL
Table 7-8 Operational State in Each Mode
○
○
○
○
○
○
○
○
○
○
○
○
○
○
SLEEP
STOP
Mode
IDLE
Under development
× (Note 1)
× (Note 1)
× (Note 1)
× (Note 1)
× (Note 1)
*(Note 2)
SLOW
Page48
○
○
○
○
○
○
×
○
selectable for
each module
<STBY2:0>
STBYCR0
ON/OFF
IDLE
001
010
011
×
○
○
○
○
○
○
○
○
SLEEP
×
○
×
×
×
×
×
○
○
○
○
×
×
○
* (Note 3)
STOP
×
×
×
×
×
×
×
×
×
×
×
×
×
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