TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 260

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

Internal SDA output (master B)
Internal SDA output (masterA)
12 Serial Bus Interface (SBI)
12.5.8
12.5.9
12.5.10 Lost-arbitration Detection Monitor
Interrupt Service Request and Release
Serial Bus Interface Operating Modes
SCL (line)
SDA line
When a serial bus interface interrupt request (INTSBI0) is generated, SBIxCR2 <PIN> is
cleared to “0.” While <PIN> is “0,” the SBI pulls the SCL line to the “L” level.
After transmission or reception of one data word, <PIN> is cleared to “0.” It is set to “1”
when data is written to or read from SBIxDBR. It takes a period of t
released after <PIN> is set to “1.”
In the address recognition mode (<ALS> = “0”), <PIN> is cleared to “0” when the received
slave address matches the value specified at SBIxI2CAR or when a general-call address is
received; i.e., the eight bits following the start condition are all zeros. When the program
writes “1” to SBIxCR2<PIN>, it is set to “1.” However, writing “0” does clear this bit to “0”.
SBIxCR2 <SBIM1:0> selects an operating mode of the serial bus interface. <SBIM1:0>
must be set to “10” to configure the SBI for the I
before switching the operating mode to the port mode.
The I
requires the bus arbitration procedure to ensure correct data transfer.
A master that attempts to generate the start condition while the bus is busy loses bus
arbitration, with no start condition occurring on the SDA and SCL lines. The I
arbitration takes place on the SDA line.
The arbitration procedure for two masters on a bus is shown below. Up until the point a,
Master A and Master B output the same data. At the point a, Master A outputs the “L” level
and Master B outputs the “H” level. Then Master A pulls the SDA bus line to the “L” level
because the line has the wired-AND connection. When the SCL line goes high at the point
b, the slave device reads the SDA line data, i.e., data transmitted by Master A. At this time,
data transmitted by Master B becomes invalid. This condition of Master B is called “Lost
Arbitration”. Master B releases its SDA pin, so that it does not affect the data transfer
initiated by another master. If two or more masters have transmitted exactly the same first
data word, the arbitration procedure continues with the second data word.
2
C bus has the multi-master capability (there are two or more masters on a bus), and
Fig. 12-12 Lost Arbitration
Under development
Page248
a
b
2
C bus mode. Make sure that the bus is free
Loses arbitration and sets the
internal SDA output to "1”.
LOW
for the SCL line to be
TMPM330
2
C-bus