TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 311

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

(3)
(4)
(5)
reading the data stored in the receive buffer.
waveform, which does not identical to the defined, results in the waveform error. The interrupt is
generated.
not without generating an interrupt at error detection. This can be set in the CECRCR1
<CECRIHLD> bit. To enable the setting, a timeout setting with the CECRCR1 <CECTOUT> bit is
required.
including the ACK bit is completed, CEC generates an interrupt after a reversed ACK response is
executed. “1” is set to the bits of the CECRSTAT register: the <CECRIEND> bit that indicates the
reception completion, and the bits corresponding to the detected errors.
interrupt is generated after the timeout. “1” is set to the bits of the CECRSTAT register corresponding
to the detected error.
to be free in transmission.
A receive buffer overrun interrupt is generated when the next data reception is completed before
The interrupt sets the CECRSTAT <CECRIOR> bit.
A waveform error occurs when waveform error detection is enabled in CECRCR3. Detecting a
The interrupt sets the CECRSTAT <CECRIWAV> bit.
You can specify if a maximum cycle error, a buffer overrun and a waveform error are suspended or
Under suspend-enable condition, if CEC keeps receiving the next bit and the entire reception
If the reception of the next bit is interrupted, CEC starts to measure the timeout period, and an
The timeout is measured from the end of the last bit received as is the case with wait time of a bus
Receive Buffer Overrun
Waveform Error
Suspending Receive Error Interrupt
Beginning of ACK bit
Under development
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2.0ms
End of “0”
output
0.3ms
Detection period
TMPM330