TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 345

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

AN11(PD7)
AN0 (PC0)
15 Analog/Digital Converter
A 10-bit, sequential-conversion analog/digital converter (A/D converter) is built into the TMPM330. This A/D
converter is equipped with 12 analog input channels.
Fig. 15-1 shows the block diagram of this A/D converter.
These 12 analog input channels (pins AN0 through AN11) are also used as input/ output ports.
AN4(PD0)
VREFH
(AVSS)
VREFL
(Note) If it is necessary to reduce a power current by operating the TMPM330 in IDLE or
Channel select
STOP mode and if either case shown below is applicable, you must first stop the A/D
converter and then execute the instruction to put the TMPM330 into standby mode:
1) The TMPM330 must be put into IDLE mode when ADMOD1<I2AD> is "0."
2) The TMPM330 must be put into STOP mode.
control circuit
ADMOD1
Internal data bus
VREF
ADSCN
Sample hold
Normal A/D conversion
Fig. 15-1 A/D Converter Block Diagram
ADMOD0
end
ADS
control circuit
busy
Under development
Comparator
+
−
scan
repeat
Interval
interrupt
Page333
D/A converter
ADMOD2
Internal data bus
conversion control
High priority AD
End
High priority AD conversion
ADREG08H~7FH
ADREG08L~7FL
AD conversion
Busy
AD conversion
result register
result register
completion interrupt
ADREGSP
AD monitor function
control
ADMOD3,5
start
HPADCE
Interrupt request INTAD
Internal data bus
AD start control
AD monitor function
ADMOD4
interrupt
TMPM330
INTADM0,1
TB0/CTRG
INTAD
ADTRG
(disabled)