TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 383
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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PAGER
A
read-modify-
write
operation
cannot be
performed.
(Note) Keep the setting order of <ENATMR>, <ENAAML> and <INTENA> as shown in
Bit symbol
Read/Write
After reset
Function
(10) PAGE register (for PAGE0/1)
the example below. Ensure an interval of time between Clock/Alarm and
interrupt.
Example: Clock setting/Alarm setting
PAGER
PAGER
0: Disabled
1: Enabled
INTRTC
INTENA
R/W
7
0
← 0 0 0 0 1 1 0 0
← 1 0 0 0 1 1 0 0
7 6 5 4 3 2 1 0
6
“0” is read.
―
R
0
Under development
5
Page371
ADJUST
PAGE
[Write]
0: Don’t care
1:
ADJUST
request
[Read]
0:
ADJUST
request
1:
requested
ADJUST
R/W
ADJUST
4
0
Enables Clock and alarm
Enables interrupt
Sets
No
Clock
0: Disabled
1: Enabled
0
1
0
1
ENATMR
3
Undefined
Selects Page0
Selects Page1
Don’t care
Adjusts seconds. The request is sampled when
the sec. counter counts up.
If the time elapsed is between 0 and 29
seconds, the sec. counter is cleared to “0”. If
the time elapsed is between 30 and 59
seconds, the min. counter is carried and sec.
counter is cleared to "0".
shows if ADJUST is requested or not.
R/W
ALARM
0: Disabled
1: Enabled
ENAALM
2
“0” is read.
―
1
R
0
Reading this bit
PAGE
selection
TMPM330
PAGE
R/W
0
0
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