TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 228
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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Price
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11 Serial Channel (SIO)
11.5 Operation in Each Mode
11.5.1
Mode 0 (I/O interface mode)
Mode 0 consists of two modes, the “SCLK output” mode to output synchronous clock and
the “SCLK input” mode to accept synchronous clock from an external source. The following
operational descriptions are for the case use of FIFO is disabled. For details of FIFO
operation, refer to the previous sections describing receive/transmit FIFO functions.
Transmitting data
SCLK output mode
In the SCLK output mode, if SC0MOD2<WBUF> is set to “0” and the transmit double
buffers are disabled, 8 bits of data are output from the TXD0 pin and the synchronous
clock is output from the SCLK0 pin each time the CPU writes data to the transmit buffer.
When all data is output, the INTTX0 interrupt is generated.
If SC0MOD2 <WBUF> is set to “1” and the transmit double buffers are enabled, data is
moved from Transmit Buffer 2 to Transmit Buffer 1 when the CPU writes data to
Transmit Buffer 2 while data transmission is halted or when data transmission from
Transmit Buffer 1 (shift register) is completed. When data is moved from Transmit
Buffer 2 to Transmit Buffer 1, the transmit buffer empty flag SC0MOD2 <TBEMP> is
set to “1,” and the INTTX0 interrupt is generated. If Transmit Buffer 2 has no data to be
moved to Transmit Buffer 1, the INTTX0 interrupt is not generated and the SCLK0
output stops.
Under development
Page216
TMPM330
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