TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 416

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

18 Flash Memory Operation
1)
1. The 1st byte specifies which one of the two serial operation modes is used. For a
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2. The 2nd byte, transmitted from the target board to the controller, is an acknowledge
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detailed description of how the serial operation mode is determined, see Determination
of a Serial Operation Mode described later. If it is determined as UART mode, the boot
program then checks if the SIO0 is programmable to the baud rate at which the 1st
byte was transferred. During the first-byte interval, the RXE bit in the HSC0MOD
register is cleare
response to the 1st byte. The boot program echoes back the first byte: 86H for UART
mode and 30H for I/O Interface mode.
To communicate in UART mode
Send, from the controller to the target board, 86H in UART data format at the desired
baud rate. If the serial operation mode is determined as UART, then the boot program
checks if the SIO0 can be programmed to the baud rate at which the first byte was
transferred. If that baud rate is not possible, the boot program aborts, disabling any
subsequent communications.
To communicate in I/O Interface mode
Send, from the controller to the target board, 30H in I/O Interface data format at 1/16
of the desired baud rate. Also send the 2nd byte at the same baud rate. Then send all
subsequent bytes at a rate equal to the desired baud rate.
In I/O Interface mode, the CPU sees the serial receive pin as if it were a general input
port in monitoring its logic transitions. If the baud rate of the incoming data is high or
the chip’s operating frequency is high, the CPU may not be able to keep up with the
speed of logic transitions. To prevent such situations, the 1st and 2nd bytes must be
transferred at 1/16 of the desired baud rate; then the boot program calculates 16 times
that as the desired baud rate. When the serial operation mode is determined as I/O
Interface mode, the SIO0 is configured for SCLK Input mode. Beginning with the third
byte, the controller must ensure that its AC timing restrictions are satisfied at the
selected baud rate. In the case of I/O Interface mode, the boot program does not
check the receive error flag; thus there is no such thing as error acknowledge (bit 3,
x8H).
UART mode
If the SIO0 can be programmed to the baud rate at which the 1st byte was transferred,
the boot program programs the SC0BRCR and sends back 86H to the controller as an
acknowledge. If the SIO0 is not programmable at that baud rate, the boot program
simply aborts with no error indication. Following the 1st byte, the controller should
allow for a time-out period of five seconds. If it does not receive 86H within the allowed
time-out period, the controller should give up the communication. The boot program
sets the RXE bit in the SC0MOD0 register to enable reception (1) before loading the
SIO transmit buffer with 86H.
I/O Interface mode
The boot program programs the SC0MOD0 and SC0CR registers to configure the
SIO0 in I/O Interface mode (clocked by the rising edge of SCLK0), writes 30H to the
RAM Transfer Command (See Table 18-6)
Under development
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TMPM330