TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 304

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13 Consumer Electronics Control (CEC)
(3)
(4)
(5)
(6)
(7)
of -4 to +3 cycles from the maximum or minimum time set in the CEC standard.
bit. The received data is discarded.
1.05 ms from the bit start point.
an ACK response to the data block when destination address corresponds with the address set in
the logical address register.
detecting the addresses corresponding.
error, buffer overrun and waveform error) is suspended or not.
response is executed by a reversed logic. If the subsequent bits are interrupted, it is determined as a
timeout, based on the setting in <CECTOUT> of the CECRCR1 register. After the ACK response or
the timeout determination, an interrupt is generated.
CECRCR1 <CECRIHLD>, is valid.
Configure the CECRCR1 <CECMIN2:0> <CECMAX2:0> bits to detect a cycle error.
You can specify the time to detect a cycle error for each sampling clock cycle between the ranges
Detecting an error during data reception causes an error interrupt, and CEC waits for the next start
Configure the CECRCR1 <CECDAT> bit for the point of determining the data as “0” or “1”.
You can specify it per two sampling clock cycles between the ranges of + or - 6 cycles with approx.
Configuring the CECRCR1 <CECACKDIS> bit enables you to specify if logical “0” is sent or not as
The header block sends logical “0” as an ACK response regardless of the bit setting when
Configure the CECRCR1 <CECRIHLD> bit to specify if a receive error interrupt (maximum cycle
Setting “1” generates no interrupt at the error detection. If data continues to the ACK bit, an ACK
Configure the CECRCR１<CECTOUT> bit to specify the time to determine a timeout.
This is used when the setting of a receive error interrupt suspension, which is specified in
Cycle Error
Point of Determining Data
ACK Response
Receive Error Interrupt Suspend
Cycles to Identify Timeout
Under development
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TMPM330