TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 236

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11 Serial Channel (SIO)
TMPM330
Under development
SCLK input mode
In the SCLK input mode with SC0MOD2 <WBUF> set to “0” and the transmit double
buffers are disabled (double buffering is always enabled for the receive side), 8-bit
data written in the transmit buffer is output from the TXD0 pin and 8 bits of data is
shifted into the receive buffer when the SCLK input becomes active. The INTTX0
interrupt is generated upon completion of data transmission and the INTRX0 interrupt
is generated at the instant the received data is moved from receive buffer 1 to receive
buffer 2. Note that transmit data must be written into the transmit buffer before the
SCLK input for the next frame (data must be written before the point A in Fig. 11-15).
As double buffering is enabled for data reception, data must be read before completing
reception of the next frame data.
If SC0MOD2 <WBUF> = “1” and double buffering is enabled for both transmission and
reception, the interrupt INTRX0 is generated at the timing Transmit Buffer 2 data is
moved to Transmit Buffer 1 after completing data transmission from Transmit Buffer 1.
At the same time, the 8 bits of data received is shifted to buffer 1, it is moved to receive
buffer 2, and the INTRX0 interrupt is generated. Upon the SCLK input for the next
frame, transmission from Transmit Buffer 1 (in which data has been moved from
Transmit Buffer 2) is started while receive data is shifted into receive buffer 1
simultaneously. If data in receive buffer 2 has not been read when the last bit of the
frame is received, an overrun error occurs. Similarly, if there is no data written to
Transmit Buffer 2 when SCLK for the next frame is input, an under-run error occurs.
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