TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 77

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8.5.1.5
No.
43
44
45
46
47
48
49
CPU detects an interrupt request when an interrupt signal changes from “L” to “H”. Interrupt signals
directly sent from peripheral functions to the CPU are configured to output “H” to indicate an
interrupt request.
Interrupt requests from interrupt pins can be set as level-sensitive (“H” or “L”) or edge-triggered
(rising or falling).
register is also required. Enable the IMCGx<INTxEN> bit and specify the active state in the
IMCGx<EMCG2:0> bits. You must set the active state for interrupt requests from each peripheral
function as shown in Table 8-2.
level.
not used for clearing a standby mode. However, an “H” pulse or “H”-level signal must be input so
that the CPU can detect it as an interrupt request.
(Note) For the CEC reception/transmission, remote control signal reception and real time
Interrupt requests from interrupt pins can be used without setting the clock generator if they are
The active state indicates which change in signal of an interrupt source triggers an interrupt. The
Interrupt requests from peripheral functions are set as rising-edge or falling-edge triggered.
If an interrupt source is used for clearing a standby mode, setting the relevant clock generator
Active State
An interrupt request detected by the clock generator is notified to the CPU with a signal in “H”
INTCAP20
INTCAP21
INTCAP30
INTCAP31
INTCAP40
INTCAP41
INTAD
clock timer interrupts, set the <INTxEN>bit to “1” and specify the active state as
shown in Table 8-2, even when they are not used for clearing a standby mode.
Table 8-2 List of Hardware Interrupt Sources (2/2)
16bit TMRB input capture 20
16bit TMRB input capture 21
16bit TMRB input capture 30
16bit TMRB input capture 31
16bit TMRB input capture 40
16bit TMRB input capture 41
A/D conversion completion
Interrupt Sources
Under development
Page65
(Clearing standby)
Active state
Generator
Clock
TMPM330