TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 261
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
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A master compares the SDA bus line level and the internal SDA output level at the rising of the SCL line. If
there is a difference between these two values, Arbitration Lost occurs and SBIxSR <AL> is set to “1”.
12.5.11 Slave Address Match Detection Monitor
12.5.12 General-call Detection Monitor
12.5.13 Last Received Bit Monitor
Master
Master
A
B
Fig. 12-13 Example of Master B Lost Arbitration (D7A = D7B, D6A = D6B)
When <AL> is set to “1,” SBIxSR <MST, TRX> are cleared to “0,” causing the SBI to operate
as a slave receiver. <AL> is cleared to “0” when data is written to or read from SBIxDBR or
data is written to SBIxCR2.
When the SBI operates as a slave device in the address recognition mode (SBIxI2CAR
<ALS> = ”0”), SBIxSR <AAS> is set to “1” on receiving the general-call address or the slave
address that matches the value specified at SBIxI2CAR. When <ALS> is “1,” <AAS> is set
to “1” when the first data word has been received. <AAS> is cleared to “0” when data is
written to or read from SBIxDBR.
When the SBI operates as a slave device, SBIxSR <AD0> is set to “1” when it receives the
general-call address; i.e., the eight bits following the start condition are all zeros. <AD0> is
cleared to “0” when the start or stop condition is detected on the bus.
SBIxSR <LRB> is set to the SDA line value that was read at the rising of the SCL line. In the
acknowledgment mode, reading SBIxSR <LRB> immediately after generation of the
INTSBIx interrupt request causes ACK signal to be read.
Internal SCL
output
Internal SDA
output
Internal
SCLoutput
Internal SDA
output
Access to SBIxDBR or
SBIxCR2
<AL>
<MST>
<TRX>
D7A
D7B
1
1
D6B
D6A
2
2
Under development
D5A D4A D3A D2A D1A D0A
Page249
3
3
Internal SDA output is fixed to “H”
due to Arbitration Lost of Master B.
4
4
5
Clock output stops here
6
7
8
9
D7A’ D6A’ D5A’ D4A’
1
2
TMPM330
3
4
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