TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 425
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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(Note) If the serial operation mode is determined as UART, the boot program checks if the SIO can
(Note) The upper four bits of the ACK response are the same as those of the previous command
(Note) The upper four bits of the ACK response are the same as those of the operation command
5)
Acknowledge Responses
The boot program represents processing states with specific codes. Table 18-10 to Table 18-13 show
the values of possible acknowledge responses to the received data. The upper four bits of the
acknowledge response are equal to those of the command being executed. Bit 3 of the code indicates
a receive error. Bit 0 indicates an invalid command error, a checksum error or a password error. Bit 1
and bit 2 are always 0. Receive error checking is not done in I/O Interface mode.
be programmed to the baud rate at which the operation mode byte was transferred. If that
baud rate is not possible, the boot program aborts, without sending back any response.
code.
code. It is 1 ( N=RAM transfer command data [7:4] ) when password error occurs.
0x?8 (See Note)
0x?1 (See Note)
0xN8 (See Note)
0xN1 (See Note)
0xN0 (See Note)
Return Value
Return Value
Return Value
Return Value
54H
4FH
4CH
0x86
0x30
0x10
0x20
0x30
0x40
Table 18-13 ACK Response to Chip and Protection Bit Erase Byte
Table 18-10 ACK Response to the Serial Operation Mode Byte
Table 18-12 ACK Response to the Checksum Byte
Table 18-11 ACK Response to the Command Byte
The Chip Erase enabling command was received.
The Chip Erase command was completed.
The Chip Erase command was abnormally completed.
The SIO can be configured to operate in UART mode. (See Note)
The SIO can be configured to operate in I/O Interface mode.
A receive error occurred while getting a command code.
An undefined command code was received. (Reception was completed normally.)
The RAM Transfer command was received.
The Show Flash Memory Sum command was received.
The Show Product Information command was received.
The Chip Erase command was received.
A receive error occurred.
A checksum or password error occurred.
The checksum was correct.
Under development
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Meaning
Meaning
Meaning
Meaning
TMPM330
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