TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 371
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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16.3 Control Registers
16.3.1
The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
1.
2.
3.
To change the status of the watchdog timer from "disable" to "enable," set the <WDTE> bit to "1".
Setting this bit to "1" enables the watch dog timer to be reset when a runaway is detected. Since a
reset initializes this bit to "1," a counter overflow causes a reset.
This is a 2-bit register for specifying the watchdog timer interrupt time for runaway detection. When
a reset is effected, this register is initialized to WDMOD <WDTP1, 0> = "00." Fig. 16-4 shows the
detection time of the watchdog timer.
When resetting, WDMOD <WDTE> is initialized to "1" and the watchdog timer is enabled.
To disable the watchdog timer, this bit must be set to "0" and, at the same time, the disable code
(B1H) must be written to the WDCR register. This dual setting is intended to minimize the
probability that the watchdog timer may inadvertently be disabled if a runaway occurs.
Watchdog Timer Mode Register (WDMOD)
Specifying the detection time of the watchdog timer <WDTP1: 0>
Enabling/disabling the watchdog timer <WDTE>
Watchdog timer out reset connection <RESCR>
Under development
Page359
TMPM330
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