TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 301
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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13.2.14 Transmit Interrupt Status Register [CECTSTAT]
<CECTIUR>:
<CECTIACK>: Indicates one of the following conditions occurs.
<CECTIAL>:
<CECTIEND>: Indicates data transmission including the EOM bit is completed.
<CECTISTA>: Indicates 1 byte of data transmission is started.
(Note)
bit Symbol
Read/Write
After reset
Function
Writing to this bit is ignored.
Indicates next data has not set to the transmission buffer within a byte of data
transmission.
・When logical “0” is not detected in transmission to the specific address.
・When logical “1” is not detected in transmission of a broadcast message .
Indicates “0” is detected while transmitting “1”.
“0” is read.
7
―
6
R
0
Under development
Page289
5
Interrupt
flag
1:
Transmit
buffer
underrun
CECTIUR CECTIACK CECTIAL CECTIEND CECTISTA
4
R
0
Interrupt
flag
1:
ACK error
detection
R
3
0
Interrupt
flag
1:
Arbitation
lost
occurs
2
R
0
Interrupt
flag
1:
data
transmissi
on
complete
d
1
R
0
is
TMPM330
Interrupt
flag
1:
Start
transmissi
on
0
R
0
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