D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 120

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Instruction
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
STC.L SSR,@–Rn
STC.L SPC,@–Rn
STC.L R0_BANK,
STC.L R1_BANK,
STC.L R2_BANK,
STC.L R3_BANK,
STC.L R4_BANK,
STC.L R5_BANK,
STC.L R6_BANK,
STC.L R7_BANK,
STS
STS
STS
STS.L MACH,@–Rn
STS.L MACL,@–Rn
STS.L PR,@–Rn
TRAPA #imm
Note:
Rev. 5.0, 09/03, page 72 of 806
*
@–Rn
@–Rn
@–Rn
@–Rn
@–Rn
@–Rn
@–Rn
@–Rn
MACH,Rn
MACL,Rn
PR,Rn
Number of states before the chip enters the sleep state.
The table shows the minimum number of clocks required for execution. In practice, the
number of execution cycles will be increased if there is contention between an instruction
fetch and a data access, or if the destination register of a load instruction (memory
register) is also used by the following instruction.
Operation
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
Rn–4
MACH
MACL
PR
Rn–4
Rn–4
Rn–4
PC
imm << 2
VBR + H'0100
Rn
SPC, SR
Rn, SR
Rn, GBR
Rn, VBR
Rn, SSR
Rn, SPC
Rn, R0_BANK
Rn, R1_BANK
Rn, R2_BANK
Rn, R3_BANK
Rn, R4_BANK
Rn, R5_BANK
Rn, R6_BANK
Rn, R7_BANK
Rn, MACH
Rn, MACL
Rn, PR
Rn
Rn
TRA,
PC
SSR,
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
Code
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0100nnnn00110011
0100nnnn01000011
0100nnnn10000011
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Privileged
Mode
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Cycles T Bit
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
8
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