D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 77
![IC SUPER H MPU ROMLESS 208QFP](/photos/12/31/123145/d6417729rhf200bv_sml.jpg)
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
EVERLIGHT
Quantity:
1 000
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Details of the status register (SR) when STC/LDC instructions are used are shown below.
1. When the DSP is not operating, operation is the same as for the SH-3.
2. In privileged DSP mode, operation is the same as in privileged mode.
3. In user DSP mode, SR can be read with an STC instruction.
4. In user DSP mode, an LDC instruction can be issued for SR, but in this case DSP-related bits
Table 2.2
Field
MD
RB
BL
RC
[11:0]
DSP
DMX
DMY
Q
M
I[3:0]
RF[1:0]
S
T
Legend
S (STC): Store SR to Rn,SR->Rn
L (LDC): Load Rn to Sr,Rn->SR
OK: STC/LDC operation is enabled.
Invalid instruction: Exception occurs when an invalid instruction is executed.
NG: Previous value is retained. No change.
are not write-protected.
Privileged
Mode
MD = 1 &
DSP = 0
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
Operation of SR Bits in Each SH-3 DSP Mode
User Mode
MD = 0 &
DSP = 0
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
S, L: Invalid
instruction
Privileged
DSP Mode
MD = 1 &
DSP = 1
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
S: OK, L: OK
User DSP
Mode
MD = 0 &
DSP = 1
S: OK, L: NG
S: OK, L: NG
S: OK, L: NG
S: OK, L: OK
S: OK, L: NG
S: OK, L: OK
S: OK, L: OK
S: OK, L: NG
S: OK, L: NG
S: OK, L: NG
S: OK, L: OK
S: OK, L: NG
S: OK, L: NG
Rev. 5.0, 09/03, page 29 of 806
Access to
DSP-Related
Bit with
Dedicated
Instruction
SETRC
instruction
SETRC
instruction
Initial Value after
Reset
1
1
1
000000000000
0
0
0
x
x
1111
x
x
x
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