D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 254

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 7 and 6—CPU Cycle/DMAC Cycle Select B (CDB1, CDB0): Select a CPU cycle or
DMAC cycle as the bus cycle of the channel B break condition.
Bit 7: CDB1
0
*
1
Note: * Don’t care.
Bits 5 and 4—Instruction Fetch/Data Access Select B (IDB1, IDB0): Select an instruction fetch
cycle or data access cycle as the bus cycle of the channel B break condition.
Bit 5: IDB1
0
1
Bits 3 and 2—Read/Write Select B (RWB1, RWB0): Select a read cycle or write cycle as the
bus cycle of the channel B break condition.
Bit 3: RWB1
0
1
Bits 1 and 0—Operand Size Select B (SZB1, SZB0): Select the operand size of the bus cycle for
the channel B break condition.
Bit 1: SZB1
0
1
Rev. 5.0, 09/03, page 206 of 806
Bit 6: CDB0
0
1
0
Bit 4: IDB0
0
1
0
1
Bit 2: RWB0
0
1
0
1
Bit 0: SZB0
0
1
0
1
Description
Condition comparison is not performed
Break condition is CPU cycle
Break condition is DMAC cycle
Description
Condition comparison is not performed
Break condition is instruction fetch cycle
Break condition is data access cycle
Break condition is instruction fetch cycle or data access cycle
Description
Condition comparison is not performed
Break condition is read cycle
Break condition is write cycle
Break condition is read cycle or write cycle
Description
Break condition does not include operand size (Initial value)
Break condition is byte access
Break condition is word access
Break condition is longword access
(Initial value)
(Initial value)
(Initial value)