D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 239

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Icyc:
Bcyc: Duration of one CKIO cycle.
Pcyc: Duration of one cycle of peripheral clock supplied to peripheral modules.
Notes: 1. S also includes the memory access wait time.
Item
Response
time
Duration of one cycle of internal clock supplied to CPU.
2. The internal clock:CKIO:peripheral clock ratio is 2:1:1.
3. The internal clock:CKIO:peripheral clock ratio is 4:1:1.
4. IRQ mode
5. Modules: TMU, RTC, SCI, WDT, REFC
6. Modules: DMAC, ADC, IrDA, SCIF
The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the
memory access is a cache-hit, this requires seven instruction execution cycles. When
the external access is performed, the corresponding number of cycles must be added.
There are also instructions that perform two external memory accesses; if the external
memory access is slow, the number of instruction execution cycles will increase
accordingly.
Total
Minimum
case *
Maximum
case *
2
3
NMI
(5.5 + X)
+ 0.5
+ 0.5
7.5
8.5 + S
Icyc
Pcyc
Bcyc
IRQ
(5.5 + X)
+ 1
4.5
16.5
26.5 + S
Icyc
Number of States
Bcyc +
Pcyc *
4
PINT
(5.5 + X)
+ 3.5
Pcyc *
12.5
18.5 + S
Icyc
5
Rev. 5.0, 09/03, page 191 of 806
Peripheral
Modules
(5.5 + X)
+ 1.5
(5.5 + X)
+ 3
8.5 *
10.5 + S *
16.5 + S *
Pcyc *
Icyc
Icyc
5
/11.5 *
Pcyc *
5
5
6
6
6
Notes
At 60-MHz (CKIO
= 30) operation:
0.13–0.28 s
At 60-MHz (CKIO
= 15) operation:
0.26–0.56 s (in
case of operand
cache-hit)
At 60-MHz (CKIO
= 15) operation:
0.29–0.59 s
(when external
memory access is
performed with
wait = 0)