D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 611

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data.
Bit 4—Parity Mode (O/E E E E ): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition
and checking. The O/E setting is ignored when parity addition and checking is disabled.
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length.
When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 5: PE
0
1
Bit 4: O/E E E E
0
1
Bit 3: STOP
0
1
Description
Parity bit not added or checked
Parity bit added and checked
When PE is set to 1, an even or odd parity bit is added to transmit data,
depending on the parity mode (O/E) setting. Receive data parity is checked
according to the even/odd (O/E) mode setting.
Description
Even parity
If even parity is selected, the parity bit is added to transmit data to make an even
number of 1s in the transmitted character and parity bit combined. Receive data
is checked to see if it has an even number of 1s in the received character and
parity bit combined.
Odd parity
If odd parity is selected, the parity bit is added to transmit data to make an odd
number of 1s in the transmitted character and parity bit combined. Receive data
is checked to see if it has an odd number of 1s in the received character and
parity bit combined.
Description
One stop bit
When transmitting, a single 1-bit is added at the end of each transmitted
character.
Two stop bits
When transmitting, two 1-bits are added at the end of each transmitted character.
Rev. 5.0, 09/03, page 563 of 806
(Initial value)
(Initial value)
(Initial value)