D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 313

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.8.2
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
2. Set the type of count clock used in the CKS2–CKS0 bits of WTCSR and the initial values for
3. When the frequency control register (FRQCR) is written to, the clock stops and the processor
4. When the WDT count overflows, the CPG resumes supplying the clock and the processor
5. The counter stops at a value of H'00 or H'01. The stop value depends on the clock ratio.
10.8.3
1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the
10.8.4
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
enters standby mode temporarily. The WDT starts counting.
resumes operation. The WOVF flag in WTCSR is not set when this happens.
If the following three conditions are all met, FRQCR should not be changed when a transfer
using the DMAC is in progress.
• Bits IFC2 to IFC0 are changed.
• Bits STC2 to STC0 are not changed.
• The clock ratio is other than I :B = 1:1.
count clock in the CKS2–CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
the counter from overflowing.
type of reset specified by the RSTS bit. The counter then resumes counting.
When a reset is generated, a low level is output at the RESETOUT pin, and a high level at the
STATUS0 and STATUS1 pins. The output period is approximately 1 count clock cycle in the
case of a power-on reset, and approximately 5 peripheral clock cycles in the case of a manual
reset.
Changing the Frequency
Using Watchdog Timer Mode
Using Interval Timer Mode
Rev. 5.0, 09/03, page 265 of 806