D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 185

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Illegal slot instruction
User break point trap
DMA address error
Operations: PC and SR of the instruction that generated the exception are saved to SPC and
SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100. When an undefined instruction other than
H'Fxxx is decoded, operation cannot be guaranteed.
Conditions:
a. When undefined code in a delay slot is decoded
b. When an instruction that rewrites PC in a delay slot is decoded
c. When a privileged instruction in a delay slot is decoded in user mode
d. When a DSP instruction in a delay slot is decoded without DSP extension (SR.DSP=0)
Operations: PC of the previous delay branch instruction is saved to SPC. SR of the
instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL,
MD, and RB bits in SR are set to 1 and a branch occurs to PC
undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed.
Conditions: When a break condition set in the user break controller is satisfied
Operations: When a post-execution break occurs, PC of the next instruction after the
instruction that set the break point is set in SPC. If a pre-execution break occurs, PC of the
instruction that set the break point is set in SPC. SR when the break occurs is set in SSR.
H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs
to PC
Conditions:
a. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
b. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S
Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access
GBR with LDC/STC are not privileged instructions and therefore do not apply.
DSP instructions: LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+,
4n + 3)
VBR + H'0100. See section 8, User Break Controller, for more information.
DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn,
STS.L DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm,
RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD,
STC RS/RE/MOD, Rn, STC.L RS/RE/MOD, @-Rn,
LDRS, LDRE, SETRC, MOVS, MOVX, MOVY, Pxxx
Rev. 5.0, 09/03, page 137 of 806
VBR + H'0100. When an