D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 99
![IC SUPER H MPU ROMLESS 208QFP](/photos/12/31/123145/d6417729rhf200bv_sml.jpg)
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
EVERLIGHT
Quantity:
1 000
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 99 of 857
- Download datasheet (5Mb)
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Instruction Format
nm type
15
md type
15
nd4 type
15
nmd type
15
xxxx
xxxx
xxxx
xxxx
nnnn
xxxx
nnnn
xxxx
mmmm
mmmm
mmmm
nnnn
dddd
dddd
dddd
xxxx
0
0
0
0
Source
Operand
mmmm: register
direct
mmmm: register
indirect
mmmm: post-
increment register
indirect (multiply-
and-accumulate
operation)
nnnn: * post-
increment register
indirect (multiply-
and-accumulate
operation)
mmmm: post-
increment register
indirect
mmmm: register
direct
mmmm: register
direct
mmmmdddd:
register indirect
with displacement
R0 (register direct) nnnndddd:
mmmm: register
direct
mmmmdddd:
register indirect
with displacement
Destination
Operand
nnnn: register
direct
nnnn: register
indirect
MACH, MACL
nnnn: register
direct
nnnn: pre-
decrement register
indirect
nnnn: indexed
register indirect
R0 (register direct) MOV.B @(disp,Rm),R0
register indirect
with displacement
nnnndddd:
register indirect
with displacement
nnnn: register
direct
Rev. 5.0, 09/03, page 51 of 806
Sample Instruction
ADD
MOV.L Rm,@Rn
MAC.W @Rm+,@Rn+
MOV.L @Rm+,Rn
MOV.L Rm,@-Rn
MOV.L Rm,@(R0,Rn)
MOV.B R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.L @(disp,Rm),Rn
Rm,Rn
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