D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 82

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The DSP unit has one DSP status register (DSR). DSR holds the status of DSP data operation
results (zero, negative, and so on) and has a DC bit which is similar to the T bit in the CPU. The
DC bit indicates one of the status flags. A DSP data processing instruction controls its execution
based on the DC bit. This control affects only the operations in the DSP unit; it controls the update
of DSP registers only. It cannot control operations in the CPU, such as address register updating
and load/store operations. Control bits CS[2:0] specify the condition to be reflected in the DC bit.
Unconditional DSP type data operations, except PMULS, MOVX, MOVY and MOVS, update the
condition flags and DC bit, but no CPU instructions, including MAC instructions, update the DC
bit. Conditional DSP type instructions do not update DSR either.
DSR is assigned as a system register and the following load/store instructions are provided:
When DSR is read by an STS instruction, the upper bits (bits 31 to 8) are all 0.
Rev. 5.0, 09/03, page 34 of 806
STS DSR,Rn;
STS.L DSR,@-Rn;
LDS Rn,DSR;
LDS.L @Rn+,DSR;
MOVS.W,
MOVS.L
Figure 2.8 Connections of DSP Registers and Buses
8 bit
39
7
DSR
A0G
A1G
32
0
MOVX.W
16 bit
16 bit
MOVY.W
31
16
M0
M1
A0
A1
X0
X1
Y0
Y1
32 bit
MOVS.W,
MOVS.L
0
LDB
XDB
YDB