D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 279

IC SUPER H MPU ROMLESS 208QFP

D6417729RHF200BV

Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of D6417729RHF200BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Manufacturer:
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9.2.2
The standby control register 2 (STBCR2) is a readable/writable 8-bit register that sets the power-
down mode. STBCR2 is initialized to H'00 by a power-on reset.
Bit 7—Module Stop 9 (MSTP9): Specifies halting of the clock supply to the X/Y memory (an
on-chip peripheral module). When the MSTP9 bit is set to 1, the supply of the clock to the
memory is halted.
Bit 6—Pin MD5 to MD0 Control (MDCHG): Specifies whether or not pins MD5 to MD0 are
changed in standby mode. When this bit is set to 1, the MD5 to MD0 pin values are latched when
returning from standby mode by means of a reset or interrupt.
Bit 5— Module Stop 8 (MSTP8): Specifies halting of the clock supply to the user break
controller UBC (an on-chip peripheral module). When the MSTP8 bit is set to 1, the supply of the
clock to the UBC is halted.
Bit 0: MSTP0
0
1
Bit 7: MSTP9
0
1
Bit 6: MDCHG
0
1
Bit 5: MSTP8
0
1
Initial value:
Standby Control Register 2 (STBCR2)
R/W:
Bit:
MSTP9 MDCHG MSTP8
Description
SCI operates
Clock supply to SCI is halted
Description
X/Y memory runs
Clock supply to X/Y memory halted
Description
Pins MD5 to MD0 are not changed in standby mode
Pins MD5 to MD0 are changed in standby mode
Description
UBC runs
Clock supply to UBC is halted
R/W
7
0
R/W
6
0
R/W
5
0
MSTP7
R/W
4
0
MSTP6
R/W
3
0
Rev. 5.0, 09/03, page 231 of 806
MSTP5
R/W
2
0
MSTP4
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
(Initial value)
MSTP3
R/W
0
0

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