D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 618

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 0—Receive Data Ready (DR): Indicates that the quantity of data in the receive FIFO data
register (SCFRDR) is less than the specified receive trigger number, and that the next data has not
yet been received after the elapse of 15 etu from the last stop bit.
Bit 0: DR
0
1
Note: * This is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (etu: elementary time unit)
Bits 15 to 12—Number of Parity Errors 3 to 0 (PER3 to PER0): Indicate the quantity of data
including a parity error in the receive data stored in the receive FIFO data register (SCFRDR).
The value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR.
Bits 11 to 8—Number of Framing Errors 3 to 0 (FER3 to FER0): Indicate the quantity of data
including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to
8 represents the number of framing errors in SCFRDR.
Rev. 5.0, 09/03, page 570 of 806
Upper 8 bits:
Initial value:
R/W:
Description
Receiving is in progress, or no receive data remains in SCFRDR after receiving
ended normally
DR is cleared to 0 when the chip undergoes a power-on reset or enters standby
mode, or when software reads DR after it has been set to 1, then writes 0 to DR
Next receive data has not been received
DR is set to 1 when SCFRDR contains less data than the specified receive
trigger number, and the next data has not yet been received after the elapse of
15 etu from the last stop bit *
PER3
15
R
0
PER2
14
R
0
PER1
13
R
0
PER0
12
R
0
FER3
11
R
0
FER2
10
R
0
FER1
R
9
0
(Initial value)
FER0
R
8
0