D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 273

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.3.9
1. Only the CPU can read/write to UBC registers.
2. The UBC cannot monitor CPU and DMAC access in the same channel.
3. Notes on the specification of a sequential break are given below:
4. The change of a UBC register value is executed in the MA (memory access) stage. Therefore,
5. Note the following when specifying an instruction in repeat execution, including a repeat
6. The branch instruction should not be executed as soon as PC trace registers BRSR and BRDR
7. If a PC break and a TLB exception or error occur in the same instruction, the priority is as
a. A condition match occurs when a channel B match occurs in a bus cycle after a channel A
b. Since the CPU has a pipeline configuration, the pipeline determines the order of an
c. When the bus cycle condition for channel A is specified as a break before execution
even if the break condition matches in the instruction fetch address following the instruction in
which pre-execution break is specified as the break condition, no break occurs. In order to
ascertain the timing of a UBC register is change, read the last register written to. Instructions
after then are valid for the newly written register value.
instruction, as the break condition: When an instruction in a repeat loop is specified as the
break condition,
a. A break is not issued during execution of a repeat loop with fewer than three instructions.
b. When an execution-times break is set, no instruction fetch from memory occurs during
are read.
follows:
a. Break and instruction fetch exceptions: Instruction fetch exception occurs first.
b. Break before execution and operand exception: Break before execution occurs first.
c. Break after execution and operand exception: Operand exception occurs first.
match occurs in another bus cycle in sequential break setting. Therefore, no condition
match occurs if a bus cycle in which a channel A match and a channel B match occur
simultaneously is set.
instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches
in the order of bus cycles, a sequential condition is satisfied.
(PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the following point must
be noted. A break is issued, and condition match flags in BRCR are set to 1, when the bus
cycle conditions both for channels A and B match simultaneously.
execution of a repeat loop with fewer than three instructions. Therefore, the value in the
execution times register, BETR, is not decremented.
Notes
Rev. 5.0, 09/03, page 225 of 806