D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 135

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 2.33 DC Bit Update Definitions
CS [2:0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Condition Mode
Carry or borrow
mode
Negative value
mode
Zero value mode
Overflow mode
Signed greater-than
mode
Signed greater-or-
equal mode
Reserved
Reserved
Description
The DC bit is set if an ALU arithmetic operation generates a carry
or borrow, and is cleared otherwise.
When a shift instruction (PSHA or PSHL) is executed, the last bit
data shifted out is copied into the DC bit.
When an ALU logical operation is executed, the DC bit is always
cleared.
When an ALU arithmetic operation or arithmetic shift (PSHA)
operation is executed, the MSB of the result, including the guard
bits, is copied into the DC bit.
When an ALU logical operation or logical shift (PSHL) operation is
executed, the MSB of the result, excluding the guard bits, is copied
into the DC bit.
The DC bit is set if the result of an ALU arithmetic or shift operation
is all-zeros, and is cleared otherwise.
The DC bit is set if the result of an ALU arithmetic operation or
arithmetic shift (PSHA) operation exceeds the destination register
range, excluding the guard bits, and is cleared otherwise.
When an ALU logical operation or logical shift (PSHL) operation is
executed, the DC bit is always cleared.
This mode is similar to signed greater-or-equal mode, but DC is
cleared if the result is all-zeros.
DC = ~{(negative value ^ over-range) | zero value};
DC = 0; In case of logical operation
If the result of an ALU arithmetic operation or arithmetic shift
(PSHA) operation exceeds the destination register range, including
the guard bits (ìoverrangeî), the definition is the same as in
negative value mode. If the result is not over-range, the definition is
the negative value mode with the DC bit inverted.
When an ALU logical operation or logical shift (PSHL) operation is
executed, the DC bit is always cleared.
DC = ~(negative value ^ over-range);
DC = 0 ; In case of logical operation
In case of arithmetic operation
In case of arithmetic operation
Rev. 5.0, 09/03, page 87 of 806