D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 89

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2.4
2.4.1
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions
Addressing
Mode
Register
direct
Register
indirect
Register
indirect with
post-increment
Register
indirect with
pre-decrement
Instruction Formats
CPU Instruction Addressing Modes
Instruction
Format
Rn
@Rn
@Rn+
@–Rn
Effective Address Calculation Method
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn − 1/2/4
+
−
Rn − 1/2/4
Rn
Rn
Rev. 5.0, 09/03, page 41 of 806
Calculation
Formula
—
Rn
Rn
After instruction
execution
Byte: Rn + 1
Word: Rn + 2
Longword: Rn + 4
Byte: Rn – 1
Word: Rn – 2
Longword: Rn – 4
(Instruction
executed with Rn
after calculation)
Rn
Rn
Rn
Rn
Rn
Rn