D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 354
![IC SUPER H MPU ROMLESS 208QFP](/photos/12/31/123145/d6417729rhf200bv_sml.jpg)
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Price
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
EVERLIGHT
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Part Number:
D6417729RHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
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11.3
11.3.1
The SH7729R supports both big endian, in which the 0 address is the most significant byte in the
byte data, and little endian, in which the 0 address is the least significant byte. Switching between
the two is designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-
on reset, big endian is engaged when MD5 is low; little endian is engaged when MD5 is high.
Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus
widths (word and longword) for synchronous DRAM. For the PCMCIA interface, choose from
byte and word. This means data alignment is done by matching the device’s data width and
endian. The access unit must also be matched to the device’s bus width. This also means that when
longword data is read from a byte-width device, four read operations must be performed. In the
SH7729R, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 11.7 to 11.12 show the relationship between endian, device data width, and access unit.
Table 11.7 32-Bit External Device/Big-Endian Access and Data Alignment
Operation
Byte access
at 0
Byte access
at 1
Byte access
at 2
Byte access
at 3
Word access
at 0
Word access
at 2
Longword
access at 0
Rev. 5.0, 09/03, page 306 of 806
BSC Operation
Endian/Access Size and Data Alignment
D31–D24
Data
7–0
—
—
—
Data
15–8
—
Data
31–24
D23–D16
—
Data
7–0
—
—
Data
7–0
—
Data
23–16
Data Bus
D15–D8
—
—
Data
7–0
—
—
Data
15–8
Data
15–8
D7–D0
—
—
—
Data
7–0
—
Data
7–0
Data
7–0
W W W W E E E E 3 3 3 3 ,
DQMUU
Asserted
Asserted
Asserted
W W W W E E E E 2 2 2 2 ,
DQMUL
Asserted
Asserted
Asserted
Strobe Signals
W W W W E E E E 1 1 1 1 ,
DQMLU
Asserted
Asserted
Asserted
W W W W E E E E 0 0 0 0 ,
DQMLL
Asserted
Asserted
Asserted
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