D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 253

IC SUPER H MPU ROMLESS 208QFP

D6417729RHF200BV

Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of D6417729RHF200BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Manufacturer
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Price
Part Number:
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EVERLIGHT
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Part Number:
D6417729RHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
8.2.8
Break bus cycle register B (BBRB) is a 16-bit readable/writable register that specifies (1) logic or
internal bus (L or I bus), X bus, or Y bus, (2) CPU cycle or DMAC cycle, (3) instruction fetch or
data access, (4) read/write, and (5) operand size in the break conditions of channel B. BBRB is
initialized to H'0000 by a power-on reset.
Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 9—X/Y Memory Bus Enable (XYE): Selects the logic or internal bus (L or I bus) or X/Y
memory bus as the bus of the channel B break condition.
Bit 8—X or Y Memory Bus Select (XYS): Selects the X bus or the Y bus as the bus of the
channel B break condition.
Bit 9: XYE
0
1
Bit 8: XYS
0
1
Initial value:
Initial value:
Break Bus Cycle Register B (BBRB)
R/W:
R/W:
Bit:
Bit:
Description
Internal bus (I bus) selected for the channel B break condition
X/Y memory bus (X/Y bus) selected for the channel B break condition
Description
X bus selected for the channel B break condition
Y bus selected for the channel B break condition
CDB1
R/W
15
R
0
7
0
CDB0
R/W
14
R
0
6
0
IDB1
R/W
13
R
0
5
0
IDB0
R/W
12
R
0
4
0
RWB1
R/W
11
R
0
3
0
Rev. 5.0, 09/03, page 205 of 806
RWB0
R/W
10
R
0
2
0
SZB1
XYE
R/W
R/W
9
0
1
0
SZB0
XYS
R/W
R/W
8
0
0
0

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