D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 183

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

TLB protection exception
PC and SR of the instruction that generated the exception are saved to SPC and SSR,
respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception
occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC
TLB protection exception in repeat loop
SR of the instruction that generated the exception is saved to SSR, but SPC is not the PC of the
instruction that generated the exception. A repeat loop cannot be restarted after returning from
the exception handler. In order to complete a repeat loop, ensure that a TLB exception or CPU
address error does not occur in the last several instructions of the repeat loop (see section 3.5.6,
MMU Exception in Repeat Loop). If a TLB protection exception occurs in an instruction
immediately before or during a repeat loop, H'0D0 is set in EXPEVT. The BL, MD, and RB
bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
CPU address error
Conditions: When a hit access violates the TLB protection information (PR bits) shown
below:
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
Conditions: TLB protection exception in the last several instruction of a repeat loop (see
section 3.5.6, MMU Exception in Repeat Loop)
Operations: TEA, PTEH, and RC bit in MMUCR are set in the way of the type of
exception.
Conditions:
a. Instruction fetch from odd address (4n + 1, 4n + 3)
b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
d. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF
PR
00
01
10
11
4n + 3)
Privileged mode
Only read enabled
Read/write enabled
Only read enabled
Read/write enabled
VBR + H'0100.
User mode
No access
No access
Only read enabled
Read/write enabled
Rev. 5.0, 09/03, page 135 of 806