D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 529

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

15.2.6
The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock
output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive
clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'00 by a
reset and in standby or module standby mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SCSSR) is set to 1 due to transfer of serial transmit data from SCTDR to SCTSR.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the receive data register full bit (RDRF) in the serial status register (SCSSR) is set
to 1 due to transfer of serial receive data from SCRSR to SCRDR. It also enables or disables
receive-error interrupt (ERI) requests.
Bit 7: TIE
0
1
Bit 6: RIE
0
1
Initial value:
Serial Control Register (SCSCR)
R/W:
Bit:
Description
Transmit-data-empty interrupt request (TXI) is disabled
The TXI interrupt request can be cleared by reading TDRE after it has been set
to 1, then clearing TDRE to 0, or by clearing TIE to 0.
Transmit-data-empty interrupt request (TXI) is enabled
Description
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
disabled
RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error
flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or
by clearing RIE to 0.
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
enabled
R/W
TIE
7
0
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
Rev. 5.0, 09/03, page 481 of 806
TEIE
R/W
2
0
CKE1
R/W
1
0
(Initial value)
(Initial value)
CKE0
R/W
0
0