D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 614

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): Select the SCIF clock source and enable
or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the
SCK pin can be used for serial clock output or serial clock input.
The CKE0 setting is valid only when the SCIF is operating on the internal clock (CKE1
CKE0 setting is ignored when an external clock source is selected (CKE1
the SCIF operating mode in the serial mode register (SCSMR), set CKE1 and CKE0. For further
details on selection of the SCIF clock source, see table 17.7 in section 17.3, Operation.
Bit 1: CKE1
0
1
Notes: 1. The output clock frequency is 16 times the bit rate.
17.2.7
The serial status register (SCSSR) is a 16-bit register. The upper 8 bits indicate the number of
receive errors in the SCFRDR data, and the lower 8 bits indicate the SCIF operating state.
The CPU can always read and write to SCSSR, but cannot write 1 to the status flags (ER, TEND,
TDFE, BRK, OPER, and DR). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. SCSSR is
initialized to H'0060 by a reset and in standby or module standby mode.
Note: * The only value that can be written is 0 to clear the flag.
Rev. 5.0, 09/03, page 566 of 806
Lower 8 bits:
Initial value:
2. The input clock frequency is 16 times the bit rate.
Serial Status Register (SCSSR)
R/W:
Bit 0: CKE0
0
1
0
1
R/(W) *
ER
7
0
R/(W) *
TEND
6
1
Description
Internal clock, SCK pin used for input pin (input signal is
ignored)
Internal clock, SCK pin used for clock output *
External clock, SCK pin used for clock input *
External clock, SCK pin used for clock input *
R/(W) *
TDFE
5
1
R/(W) *
BRK
4
0
FER
R
3
0
PER
R
2
0
1). Before selecting
1
2
2
R/(W) *
RDF
1
0
(Initial value)
0). The
R/(W) *
DR
0
0