D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 265

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.3.4
1. The break condition on an X/Y-memory bus cycle is specified only in channel B. If XYE in
2. When X-memory address is selected as the break condition, specify the X-memory address in
8.3.5
1. When SEQ in BRCR is set to 1, the sequential break is issued when the channel B break
2. In sequential break specification, the internal/X/Y bus can be selected and the execution times
8.3.6
When a break occurs, PC is saved to SPC in user breaks but saved to a fixed address
(H'FD000000) in the ASE space in an ASE break. The PC value saved is as follows depending on
the type of break.
1. When instruction fetch (before instruction execution) is specified as a break condition:
2. When instruction fetch (after instruction execution) is specified as a break condition:
3. When data access (address only) is specified as a break condition:
BBRB is set to 1, break address and break data on the X/Y-memory bus are selected. At this
time, select the X-memory bus or Y-memory bus by specifying XYS in BBRB. The break
condition cannot include both X-memory and Y-memory at the same time. The break
condition is applied to X/Y-memory bus cycles by specifying CPU/data access/read or
write/word or no specified operand size in the break bus cycle register B (BBRB).
the upper 16 bits of BARB and BAMRB. When Y-memory address is selected, specify the Y-
memory address in the lower 16 bits. Specification of X/Y-memory data is the same for BDRB
and BDMRB.
condition matches after the channel A break condition matches. A user break is ignored even if
the channel B break condition matches before the channel A break condition matches. When
channel A and B conditions match at the same time, a sequential break is not issued.
break condition can be also specified. For example, when the execution times break condition
is specified, the break condition is satisfied by a channel B condition match with BETR =
H'0001 after a channel A condition match.
The value of the program counter (PC) saved is the address of the instruction that matches the
break condition. The fetched instruction is not executed, and a break occurs before it.
The PC value saved is the address of the instruction to be executed following the instruction in
which the break condition matches. The fetched instruction is executed, and a break occurs
before execution of the next instruction.
The PC value is the address of the instruction to be executed following the instruction that
matched the break condition. The instruction that matched the condition is executed and the
break occurs before the next instruction is executed.
Break on X/Y-Memory Bus Cycle
Sequential Break
Value of Saved Program Counter
Rev. 5.0, 09/03, page 217 of 806