D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 206
![IC SUPER H MPU ROMLESS 208QFP](/photos/12/31/123145/d6417729rhf200bv_sml.jpg)
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number:
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6.2
The X/Y memory can be located in either a mappable area or fixed-mapped area, depending on the
mode bit (MD) and DSP bit (DSP) setting in the status register (SR). Figure 6.1 shows X/Y
memory logical mapping.
1. Privileged Mode
2. User Mode
3. Privileged-DSP Mode
4. User-DSP Mode
For the mappable area, the C (cacheable) bit in the TLB entry must be cleared to 0 to guarantee a
two-cycle access.
Mapping through TLB translation provides a flexible X/Y memory addressing scheme but takes
two cycles even when the C bit in the TLB entry is cleared to 0. Fixed mapping provides a one-
cycle access for read and two-cycle access for write, which is the appropriate method for mission-
critical realtime operations.
The X/Y memory resides in the second 16 Mbytes of physical address space area 1, from H'A500
0000 to H'A5FF FFFF. This 16-Mbyte address space is shadowed and maps to the same 128-kbyte
X/Y ROM/RAM. Figures 6.1 and 6.2 show X/Y memory physical mapping.
Rev. 5.0, 09/03, page 158 of 806
MD = 1, DSP = 0: Any physical address in space P0 or P3 can map to X/Y memory through
TLB translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the P2 space can
also fixed-map to X/Y memory. Since the DSP extension is disabled, the DSP instruction set
and registers are not available to the programmer.
MD = 0, DSP = 0: Any physical address in the U0 space can access X/Y memory through TLB
translation. Any access to addresses beyond the U0 space will cause an address error. Since the
DSP extension is disabled, the DSP instruction set and registers are not available to the
programmer.
MD = 1, DSP = 1: Any physical address in space P0 or P3 can map to X/Y memory through
TLB translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the P2 space can
also fixed-map to X/Y memory. Since the DSP extension is enabled, the DSP instruction set
and registers are available to the programmer.
MD = 0, DSP = 1: Any physical address in space U0 can map to X/Y memory through TLB
translation. Addresses ranging from H'A500 0000 to H'A5FF FFFF in the Uxy spaces can also
fixed-map to X/Y memory. Any access outside U0 and Uxy space will cause an address error.
Since the DSP extension is enabled, the DSP instruction set and registers are available to the
programmer.
X/Y Memory Access from CPU
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