D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 16

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section
11.2.13 MCS0 Control
Register (MCSCR0)
11.3.4 Synchronous
DRAM Interface
11.3.7 Waits between
Access Cycles
Figure 11.40 Waits
between Access Cycles
11.3.10 MCS[0] to
MCS[7] Pin Control
12.6 Usage Notes
14.4.3 Precautions
when Using RTC
Module Standby
Rev. 5.0, 09/03, page xiv of xlvi
Page
304
334
363
366
431,
432
470
Description
Description added
Bit 6—CS2/CS0 Select (CS2/0)
Note that the CS2/0 bit in MCSCR should always be cleared to 0
(area 0 selected).
Bank Active description added
… .In bank active mode, too, all banks become inactive after a
refresh cycle or after the bus is released as the result of bus
arbitration.
The bank active mode should not be used unless the bus width
for all areas is 32 bits.
Figure amended
CKIO
A25 to A0
Description amended
This enables 32-, 64-, 128-, or 256-Mbit memory to be connected
to area 0 or area 2. However, only CS2/0 = 0 (area 0) should be
used for MCSCR0. Table 11.15 shows MCSCR0–MCSCR7
settings and MCS[0]–MCS[7] assertion conditions.
Description added
13. DMAC transfers should not be performed in the sleep mode
14. When the following three conditions are all met, the
15. If the following three conditions are all met, big-endian
Newly added
under conditions other than when the clock ratio of I (on-
chip clock) to B (bus clock) is 1:1.
frequency control register (FRQCR) should not be changed
while a DMAC transfer is in progress.
access is used when the DMAC is used to transfer data from
XY memory, even in the little-endian mode.
Bits IFC2 to IFC0 are changed.
STC2 to STC0 in FRQCR are not changed.
The clock ratio of I (on-chip clock) to B (bus clock) after
the change is other than 1:1.
The source address for the transfer is in XY memory.
The indirect address mode is used.
The byte size data is transferred.
The data format is little-endian.
T
1
T
2
Twait
T
1
T
2
Twait
T
1
T
2