D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 180

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.4.3
When the SH7729R encounters any exception condition other than a reset or interrupt request, it
executes the following operations:
1. The contents of PC and SR are saved to SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt
3. The MD bit in SR is set to 1 to place the SH7729R in privileged mode.
4. The RB bit in SR is set to 1.
5. An encoded value identifying the exception event is written to bits 11–0 of the EXPEVT
6. Instruction execution jumps to the vector location designated by either the sum of the vector
4.5
This section describes the conditions for specific exception handling, and this LSI operations.
4.5.1
Rev. 5.0, 09/03, page 132 of 806
when the BLMSK bit is 1).
register.
base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the
vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke
the exception handler.
Power-On Reset
Manual Reset
Conditions: RESETP low
Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip peripheral
modules are initialized. See the register descriptions in the relevant sections for details. A
power-on reset must always be performed when powering on. A low level is output from
the RESETOUT pin, and a high level is output from the STATUS0 and STATUS1 pins.
Conditions: RESETM low
Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC
Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set
to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip
peripheral modules are initialized. See the register descriptions in the relevant sections for
details. A low level is output from the RESETOUT pin, and a high level is output from the
STATUS0 and STATUS1 pins.
General Exceptions
Individual Exception Operations
Resets
H'A0000000.
H'A0000000.