D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 362

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

waits. The address/CS6 setup and hold times for the read/write strobe signals can be set in the
range 0.5–7.5 using bits A6TED2–A6TED0 and A6TEH2–A6TEH0 in the PCR register.
11.3.3
Basic Interface
Basic Timing: The basic interface of the SH7729R uses strobe signal output in consideration of
the fact that mainly static RAM will be directly connected. Figure 11.6 shows the basic timing of
normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is
asserted for one cycle to indicate the start of a bus cycle. The CSn signal is negated on the T2
clock falling edge to secure the negation period. Therefore, in case of access at minimum pitch,
there is a half-cycle negation period.
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WE
signal for the byte to be written is asserted. For details, see section 11.3.1, Endian/Access Size and
Data Alignment.
Read/write for cache fill or write-back follows the set bus width and transfers a total of 16 bytes
continuously. The bus is not released during this transfer. For cache misses that occur during byte
or word operand accesses or branching to odd word boundaries, the fill is always performed by
longword accesses on the chip-external interface. Write-through-area write access and non-
cacheable read/write access are based on the actual address size.
Rev. 5.0, 09/03, page 314 of 806