D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 256

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 31 to 22—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 21—Break ASID Mask A (BASMA): Specifies whether or not channel A break bits ASID7
to ASID0 (BASA7 to BASA0) set in BASRA are masked.
Bit 21: BASMA Description
0
1
Bit 20—Break ASID Mask B (BASMB): Specifies whether or not channel B break bits ASID7
to ASID0 (BASB7 to BASB0) set in BASRB are masked.
Bit 20: BASMB Description
0
1
Bits 19 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 15—CPU Condition Match Flag A (SCMFCA): When the CPU bus cycle condition in the
break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 to this bit.
Bit 15:
SCMFCA
0
1
Bit 14—CPU Condition Match Flag B (SCMFCB): When the CPU bus cycle condition in the
break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 to this bit.
Bit 14:
SCMFCB
0
1
Rev. 5.0, 09/03, page 208 of 806
All BASRA bits are included in break condition, ASID is checked
No BASRA bits are included in break condition, ASID is not checked
All BASRB bits are included in break condition, ASID is checked
No BASRB bits are included in break condition, ASID is not checked
Description
CPU cycle condition for channel A is not matched
CPU cycle condition for channel A is matched
Description
CPU cycle condition for channel B is not matched
CPU cycle condition for channel B is matched
(Initial value)
(Initial value)
(Initial value)
(Initial value)