D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 257

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle
condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 to this bit.
Bit 12—DMAC Condition Match Flag B (SCMFDB): When the on-chip DMAC bus cycle
condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 to this bit.
Bit 11—PC Trace Enable (PCTE): Enables a PC trace.
Bit 10—PC Break Select A (PCBA): Selects the break timing of the instruction fetch cycle for
channel A as before or after instruction execution.
Bits 9 and 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Data Break Enable B (DBEB): Selects whether or not the data bus condition is included
in the channel B break condition.
Bit 13:
SCMFDA
0
1
Bit 12:
SCMFDB
0
1
Bit 11: PCTE
0
1
Bit 10: PCBA
0
1
Bit 7: DBEB
0
1
Description
DMAC cycle condition for channel A is not matched
DMAC cycle condition for channel A is matched
Description
DMAC cycle condition for channel B is not matched
DMAC cycle condition for channel B is matched
Description
PC trace disabled
PC trace enabled
Description
PC break of channel A is set before instruction execution
PC break of channel A is set after instruction execution
Description
Data bus condition not included in channel B condition
Data bus condition included in channel B condition
Rev. 5.0, 09/03, page 209 of 806
(Initial value)
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(Initial value)
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