D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 50

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 1.1
Item
CPU
DSP
Rev. 5.0, 09/03, page 2 of 806
SH7729R Features
Features
Original Renesas Technology SuperH architecture
Compatible with SH-1, SH-2, and SH-3 series at object code level
32-bit internal data bus
General-registers
RISC-type instruction set
Instruction execution time: one instruction/cycle for basic instructions
Logical address space: 4 Gbytes
Space identifier ASID: 8 bits, 256 logical address spaces
Five-stage pipeline
Mixture of 16-bit and 32-bit instructions
Multiplier, ALU, barrel shifter, and DSP register
16-bit
Large DSP data registers
Extended Harvard Architecture for DSP data bus
Max. four parallel operations: ALU, multiply, and two load or store
Two addressing units to generate addresses for two memory access
DSP data addressing modes: increment, indexing (with or without modulo
addressing)
Zero-overhead repeat loop control
Conditional execution instructions
User DSP mode and privileged DSP mode
Sixteen 32-bit general registers (eight 32-bit shadow registers)
Eight 32-bit control registers
Four 32-bit system registers
Instruction length: 16-bit fixed length for improved code efficiency
Load/store architecture
Delayed branch instructions
Instruction set based on C language
Six 32-bit data registers
Two 40-bit data registers
Two data buses
One instruction bus
16-bit
32-bit one cycle multiplier