D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 311

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select the clock to be used for the
WTCNT count from the eight types obtainable by dividing the peripheral clock. The overflow
period in the table is the value when the peripheral clock (P ) is 15 MHz.
Note: If bits CKS2–CKS0 are modified when the WDT is running, the up-count may not be
10.7.3
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
Writing to WTCNT and WTCSR: These registers must be written to using a word transfer
instruction. They cannot be written to with a byte or longword transfer instruction. When writing
to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 10.3. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as
the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
Bit 3: IOVF
0
1
Bit 2: CKS2
0
1
performed correctly. Ensure that these bits are modified only when the WDT is not running.
Notes on Register Access
0
1
0
1
Bit 1: CKS1
Description
No overflow
WTCNT has overflowed in interval timer mode
Bit 0: CKS0
0
1
0
1
0
1
0
1
Clock Division Ratio
1
1/4
1/16
1/32
1/64
1/256
1/1024
1/4096
(Initial value)
Rev. 5.0, 09/03, page 263 of 806
Overflow Period
(when P = 15 MHz)
17 s
68 s
273 s
546 s
1.09 ms
4.36 ms
17.48 ms
69.91 ms
(Initial value)