D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 188

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.6
Rev. 5.0, 09/03, page 140 of 806
Return from exception handling
Operation when exception or interrupt occurs while SR.BL
SPC when exception occurs: The PC saved to SPC when an exception occurs is as shown
below:
Initial register values after reset
Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not
guaranteed in this case.
Check the BL bit in SR with software. When SPC and SSR have been saved to external
memory, set the BL bit in SR to 1 before restoring them.
Issue an RTE instruction, which sets SPC in PC and SSR in SR, and causes a branch to the
SPC address, and return from exception handling.
Interrupt: Acceptance is suppressed until the BL bit in SR is cleared to 0. If there is an
interrupt request and the reception conditions are satisfied, the interrupt is accepted after
the execution of the instruction that clears the BL bit in SR to 0. In sleep or standby mode,
however, the interrupt will be accepted even when the BL bit in SR is 1.
Exception: No user break point trap will occur even when the break conditions are met.
When one of the other exceptions occurs, a branch is made to the fixed address of the reset
(H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are
undefined. Differently from general reset processing, the RESETOUT pin is not asserted,
and reset status is output from the STATUS0 and STATUS1 pins.
Re-executing-type exceptions: PC of the instruction that caused the exception is set in SPC
and re-executed after return from exception handling. If the exception occurred in a delay
slot, however, PC of the immediately prior delayed branch instruction is set in SPC. If the
condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is
set in SPC.
Completed-type exceptions and interrupts: PC of the instruction after the one that caused
the exception is set in SPC. If the exception was caused by a conditional delayed branch
instruction, however, the branch destination PC is set in SPC. If the condition of the
conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC.
Undefined registers
R0_BANK0/1–R7_BANK0/1, R8–R15, GBR, SPC, SSR, MACH, MACL, PR
Initialized registers
VBR = H'00000000
SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3–SR.I0 = H'F. Other SR bits are undefined.
PC = H'A0000000
Cautions
1