D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 27

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.3 BSC Operation .................................................................................................................. 306
Section 12 Direct Memory Access Controller (DMAC)
12.1 Overview ........................................................................................................................... 369
12.2 Register Descriptions......................................................................................................... 375
12.3 Operation........................................................................................................................... 387
12.4 Compare Match Timer (CMT) .......................................................................................... 420
12.5 Examples of Use................................................................................................................ 427
11.2.20 MCS7 Control Register (MCSCR7)..................................................................... 305
11.3.1 Endian/Access Size and Data Alignment ............................................................. 306
11.3.2 Description of Areas............................................................................................. 311
11.3.3 Basic Interface...................................................................................................... 314
11.3.4 Synchronous DRAM Interface ............................................................................. 321
11.3.5 Burst ROM Interface ............................................................................................ 347
11.3.6 PCMCIA Interface ............................................................................................... 350
11.3.7 Waits between Access Cycles .............................................................................. 362
11.3.8 Bus Arbitration..................................................................................................... 363
11.3.9 Bus Pull-Up .......................................................................................................... 364
11.3.10 MCS[0] to MCS[7] Pin Control ........................................................................... 366
12.1.1 Features ................................................................................................................ 369
12.1.2 Block Diagram ..................................................................................................... 371
12.1.3 Pin Configuration ................................................................................................. 372
12.1.4 Register Configuration ......................................................................................... 373
12.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)........................................... 375
12.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) .................................. 376
12.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) ......................... 377
12.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) ................................... 378
12.2.5 DMA Operation Register (DMAOR) ................................................................... 385
12.3.1 DMA Transfer Flow............................................................................................. 387
12.3.2 DMA Transfer Requests....................................................................................... 389
12.3.3 Channel Priority ................................................................................................... 391
12.3.4 DMA Transfer Types ........................................................................................... 394
12.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 407
12.3.6 Source Address Reload Function ......................................................................... 416
12.3.7 DMA Transfer Ending Conditions ....................................................................... 418
12.4.1 Overview .............................................................................................................. 420
12.4.2 Register Descriptions ........................................................................................... 421
12.4.3 Operation.............................................................................................................. 424
12.4.4 Compare Match .................................................................................................... 425
12.5.1 Example of DMA Transfer between On-Chip IrDA and External Memory ........ 427
12.5.2 Example of DMA Transfer between A/D Converter and External Memory
(Address Reload On) ............................................................................................ 428
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