D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 46

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 16.3
Table 16.4
Table 16.5
Table 16.6
Table 16.7
Table 16.8
Table 16.9
Table 17.1
Table 17.2
Table 17.3
Table 17.4
Table 17.5
Table 17.6
Table 17.7
Table 17.8
Table 17.9
Table 17.10 SCIF Interrupt Sources ........................................................................................... 594
Table 18.1
Table 18.2
Table 19.1
Table 19.2
Table 20.1
Table 20.2
Table 20.3
Table 20.4
Table 20.5
Table 20.6
Table 20.7
Table 20.8
Table 20.9
Table 20.10 Port E Data Register (PEDR) Read/Write Operations ............................................ 640
Table 20.11 Port F Register ........................................................................................................ 641
Table 20.12 Port F Data Register (PFDR) Read/Write Operations ............................................ 642
Table 20.13 Port G Register ....................................................................................................... 643
Table 20.14 Port G Data Register (PGDR) Read/Write Operations ........................................... 644
Table 20.15 Port H Register ....................................................................................................... 645
Table 20.16 Port H Data Register (PHDR) Read/Write Operations ........................................... 646
Table 20.17 Port J Register......................................................................................................... 647
Table 20.18 Port J Data Register (PJDR) Read/Write Operations.............................................. 648
Table 20.19 Port K Register ....................................................................................................... 649
Table 20.20 Port K Data Register (PKDR) Read/Write Operations ........................................... 650
Table 20.21 Port L Register........................................................................................................ 651
Rev. 5.0, 09/03, page xliv of xlvi
Register Settings for Smart Card Interface ............................................................. 541
Relationship of n to CKS1 and CKS0..................................................................... 543
Examples of Bit Rate B (Bits/s) for SCBRR Settings (n
Examples of SCBRR Settings for Bit Rate B (Bits/s) (n
Maximum Bit Rates for Frequencies (Smart Card Interface Mode) ....................... 544
Register Set Values and SCK Pin ........................................................................... 544
Smart Card Mode Operating State and Interrupt Sources....................................... 551
SCIF Pins................................................................................................................ 559
SCIF Registers ........................................................................................................ 560
SCSMR Settings ..................................................................................................... 571
Bit Rates and SCBRR Settings ............................................................................... 572
Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode) ............................................................................................ 576
Maximum Bit Rates with External Clock Input (Asynchronous Mode)................. 577
SCSMR Settings and SCIF Communication Formats ............................................ 581
SCSCR Settings and SCIF Clock Source Selection................................................ 582
Serial Communication Formats .............................................................................. 582
IrDA Pins................................................................................................................ 603
IrDA Registers ........................................................................................................ 604
List of Multiplexed Pins ......................................................................................... 609
Pin Function Controller Registers........................................................................... 613
Port A Register ....................................................................................................... 631
Port A Data Register (PADR) Read/Write Operations ........................................... 632
Port B Register........................................................................................................ 633
Port B Data Register (PBDR) Read/Write Operations ........................................... 634
Port C Register........................................................................................................ 635
Port C Data Register (PCDR) Read/Write Operations ........................................... 636
Port D Register ....................................................................................................... 637
Port D Data Register (PDDR) Read/Write Operations ........................................... 638
Port E Register........................................................................................................ 639
0)................................. 543
0)................................. 543